ĿĿ
ijĴ Cadence OrCad 9.2 Complete Suite ij
ĿĿĿ
Supplier : TEAM PANTHEON Release Date : 12/06/2000
Cracker : TEAM PANTHEON ٿ Program Type : CAD
Packager : Willi Discs : 1CD / 23 x 15MB
Protection: dONGLE ڳ Format : .bin/.cue
Ŀ Ŀ ĿĿ
Release Info:
~~~~~~~~~~~~~
In its new Orcad Release 9.2 software, Cadence PCB Systems Division
(PSD) is shipping updates to key brands, including: Orcad Capture, CIS,
Layout, and PSpice products, as well as overall Windows 2000 readiness.
Web updates and the latest enhancements will also be included on a single
CD release. Here are some of the enhancements you'll enjoy:
New FPGA Design Libraries and Design Flow Support
You're enabled for FPGA design. New libraries for all popular FPGAs and
CPLDs are now included with Capture. Design flows are verified and
documented to support Cadence VHDL Desktop and Synplicity Synplify
products. See the Cadence PSD web site
(http://mainstream.pcb.cadence.com/fpga/fpgastudio.htm) for more
information.
Vendor Place and route system
Actel Designer Series
Altera MAX+Plus II or Quartus
Atmel Atmel Integrated Development System (IDS)
Lattice Semiconductor IspDesignEXPERT
Lucent Technologies ORCA Foundry
Xilinx Alliance, Foundation, or WebFitter
Capture libraries and application notes for Quicklogic
(www.quicklogic.com) and Triscend (www.triscend.com) are also available
for download at factory web sites.
Activeparts Plug-in for SpinCircuit.com
Research and download new part data from the Internet.
www.SpinCircuit.com
enables you to search and select parts right off the Internet and place
them directly onto your schematic page, without leaving Capture.
SpinCircuit.com is the home of one million commercial and military
standard parts.
Better Control and Editing of Schematic Properties
Control of data is a breeze with Capture's new spreadsheet editor
features and reporting options. Now, you don't need to scroll across
columns to view or edit a property with the new Pivot option. Simply
invert object and property placement to show objects across the top row
and properties down the left-hand column. The ASCII Import/Export
property utility for part and net properties allows you to use external
spreadsheets or database programs to add, modify, or even calculate new
properties for your schematics.
Improvements for PSpice Users
In response to your feedback, we've implemented the top usability
requests for fast and efficient analog circuit capture, including: most
recently used (MRU) pick on menu bar, additional short-cut keys, and a
new Analog/Mixed-Signal project wizard option that enables you to use an
existing project as a template. These new features smooth the
schematic/simulator cycle.
LAYOUT:
Manual Routing and Track Editing
Single entity
Tracks now move correctly with multiple components even if off grid.
Manual route hinting provides control for preferred 135 (45) or 90 degree
angles. Vias now move using the same hinting algorithms Numerous segment
mode copper share improvements allow shared segments and vias to move as
segments. Optimized manual routing to minimize creation of acute and
90-degree angles. Segment mode treats off-grid tracks the same as on-grid
tracks. During manual routing, Layout displays a ratnest line to a
partially routed track if it is closer than any other target pad. Layout
now retains the connectivity data for copper pours and planes while
manually routing. Any angle mode with real time feedback when angles are
orthogonal or 45-degrees. Copy Route now copies based on net intelligence
rather than by net topology. Allows user to copy tracks on repeated
circuitry without having to set up matching connections ahead of time,
but still adheres to netlist and DRC. Includes test points and free vias
as well as tracks. DRC
New "Allow DRC Errors" mode allows intentional component and track
editing errors to be created with DRC markers automatically appearing and
disappearing in real time. DRC options dialog settings persistent between
sessions. Now, you can display DRC errors on invisible layers using
dotted circles Pads, Vias and Padstack Management
New user option permits moving free vias with components globally.
Now you can assign colors to Free Vias.
Improved padstack selection now allows you to select padstacks by Name,
Height/Width, Layer, Shape, or Miscellaneous properties. For instance,
you can easily pick all padstacks with 36 drill and change to 37, or pick
all pad layers with rectangular padstacks of 35 by 70. Added ability to
rotate pads and thermal reliefs. Layout now properly detects blind vias
which are drilled from opposite sides of the board at the same X-Y
location. Added ability to globally change all vias on a net to a
different type. Free Via options dialog settings persistent between
sessions. AutoECO
AutoECO now removes only the segments nearest the component pins when
removing or replacing a component during ECO. UNDO
Now you can UNDO Copy Route.
Plus you can UNDO Mincon.
Miscellaneous
Improved overall stability of Layout.
Spreadsheet items are automatically updated when selecting new objects in
design window. Incompletely drawn rotated square pads from Post Process
output, fixed. Selected components deleted when performing Remove
Violation from Board, fixed. Automatic Board Cleanup
You can now select which actions are performed when Automatic Board
Cleanup is activated. Additionally, you can choose to allow Automatic
Board Cleanup to affect locked tracks. Select from: Miter 90-degree
corners
Eliminate acute angles
Optimize Vertices
Optimize Shared Tracks
Optimize Shared Vias
Optimize pad exits
You can also eliminate unused padstacks, footprints or nets from the
design using Auto Cleanup Design. GerbTool
GerbTool design file now uses Layout's color assignments and stacks
layers appropriately for IPC-D-356-Netlist Comparison. Interface and
Translator
SPECCTRA Autorouter interface
Width by layer and clearance by layer net properties are now passed from
Layout to SPECCTRA. Layout copper areas are now enclosed by route
keepouts when passed to SPECCTRA. Vias embedded within pads are property
changed to make SPECCTRA 34 percent faster at routing. Free via handling
improved.
GenCAD interface
Added user control over test probe size and type.
Added user control over part body definition.
Added user control over test pads and test pins.
DXF interface
Generates 2D projection plots of Layout data onto customer specified
layers. Generates drill plots for blind and buried vias.
Added user control over cross-hairs in drill plots.
Microsim PCBoards translator
All customer-reported bugs have been fixed.
IDF interface
Corrected a keepout translation bug.
Corrected a mirroring/rotation bug.
Installation:
~~~~~~~~~~~~~
burn with your favorite cdr-software and install :)
when u r asked for serial... use the following:
App Serial
----------------------------------
Capture A
CaptureCIS B
LayoutStd E
LayoutPlus F
LayoutEngEd G
PSpice H
PSpiceAD I
PSpiceADBasics J
PSpiceOptimizer K
For full products u need only B,F,I,K. These includes the other ones.
After that you will asked for a authorization-code.
Write in any number but only 1 line.
|
 讓我們程式搜尋結果更加完美 如果您覺得該文件有幫助到您，煩請按下我如果您覺得該文件是一個一無是處的文件，也煩請按下我 |
|
該文件您看起來是亂碼嗎？您可以切換編碼方式試試看！ISO-8859-1 | latin1 | euc-kr | euc-jp | CP936 | CP950 | UTF-8 | GB2312 | BIG5 |
|